This invention relates to programmable logic devices, and more particularly to programmable logic devices having improved logic array blocks, and improved interconnections between macrocells within these blocks and between blocks.
Programmable logic devices are capable of being programmed to provide complex logic functions by interconnecting regions of logic of low to moderate sophistication. However, the most advanced logic can be difficult to interconnect because this involves programmably interconnecting a large number of logic terms. Unless sufficient routing resources are provided, the logic on the programmable logic device will be under-utilized. For instance, if too few conducting lines are provided or the interconnections are insufficiently flexible, all pathways between certain regions of logic may be blocked. Further, the schemes generally used for interconnecting the more basic types of logic cannot simply be scaled up to accommodate complex logic. Merely providing a larger number of conductors in substantially the same fashion as used for interconnecting rudimentary logic quickly becomes untenable with regard to circuit speed and chip "real estate."
Another consideration involves using logic that it is arranged in complex logic blocks that are based on multiple "macrocells" of logic. With this type of logic, if the macrocells themselves are sufficiently complex it becomes necessary to provide a more sophisticated macrocell interconnection scheme. Macrocells must work efficiently with the other macrocells within each logic block, which necessitates interconnections that can be flexibly routed to allow logic in each macrocell to be shared among other macrocells in the same logic block. Further, it would be advantageous if the outputs of the macrocells could be fed back as inputs to the other macrocells, as this allows relatively more complex logic functions to be provided by a single logic array block. Macrocell resources should also be available to be shared among distinct logic blocks so that logic designers are not unduly constrained by the specific number of macrocells within each block.
It is therefore an object of this invention to provide improved programmable logic devices.
It is a further object of this invention to provide improved programmable logic devices having improved programmable interconnections between improved logic array blocks that are based on advanced macrocells.